A sample-and-hold circuit is a circuit which performs sampling of an input signal by a switch element such as a MOS transistor or the like, to be held in a capacitor element for holding, and is widely used. In the sample-and-hold circuit with this type of simple configuration, there is a disadvantage in that noise picked up when sampling is performed becomes large, and S/N ratio is bad. In addition, there is a disadvantage in that crosstalk occurs between a sampling pulse signal and a hold signal.
Consequently, a sample-and-hold circuit is disclosed in which 2 switch elements for sampling are connected in parallel, and timing at which respective switch elements are turned ON is made different. For example, Patent Document 1 describes a sample-and-hold circuit which switches a time constant of a time constant switching means during a signal extraction period by control of a timing control circuit. More specifically, in a first sampling period and a second sampling period following the first sampling period, sampling is performed by changing a value (i.e., giving different value) of a resistor connected in series to each of the switch elements, and noise is reduced.
Patent Document 2 describes a sample-and-hold circuit that is provided with a first and a second transmission gate for sampling, and a delay circuit which delays a signal applied to a control input terminal of the first transmission gate, to be received by a control input terminal of the second transmission gate, and is configured such that gate width of an MOS transistor for a second transmission gate switch is smaller than gate width of an MOS transistor for a first transmission gate switch. According to this type of sample-and-hold circuit, a transmission gate configured by the MOS transistor with the small gate width is ON at an instant at which a transmission gate configured by the MOS transistor with a large gate width is OFF, and it is possible to lower impedance of a hold capacitor terminal, and reduce crosstalk of the sampling pulse signal.    [Patent Document 1]
JP Patent Kokai Publication No. JP-A-61-8799    [Patent Document 2]
JP Patent Kokai Publication No. JP-A-02-302999